Prof. Bah-Hwee Gwee
Nanyang Technological University, Singapore
Dr Bah-Hwee Gwee received his B.Eng degree from University of Aberdeen, UK, in 1990. He received his MEng and PhD degrees from Nanyang Technological University in 1992 and 1998 respectively. He was an Assistant Professor of School of EEE, NTU from 1999 to 2005. He is currently an Associate Professor in School of EEE, NTU. He has worked on a number of research projects with research grant amounting to S$8m (~US$5.7m). He was the principal investigator of the research projects from MoE Academic Research Tier-2 grant of S$1.3m (~US$860k), ASEAN-EU University Network Programme grant of €200k and the Defense Science Organization grant of S$3.25m (~US$2.32m). He was also the Co-Principal Investigator of NTU-Panasonic research collaboration amounting to S$1m (~US$800k) and DARPA project of ~US$350k, Linkoping University – NTU joint research collaboration of S$660k (~US$400k), The Agency for Science, Technology and Research (A*STAR) – PSF research project of S$700k ((USD500k). His research interests include low power asynchronous IC design, Class-D amplifiers, digital signal processing and soft computing. He has published more than 100 technical papers, 6 patents (3 granted in USA) and started a Start-up Company in 2005.
He was the Chairman of IEEE-Singapore Circuits and Systems Chapter in 2005, 2006, 2013 and 2016. He is the Chairman of IEEE Circuits and Systems Society – DSPTC (2019-2020). He was the General Co-Chair of IEEE DSP 2018 and IEEE SOCC 2019. He was the organizing committee of the IEEE Bio-CAS 2004, IEEE APCCAS 2006 and the TPC Chair of International Symposium on Integrated Circuits (ISIC 2007, ISIC 2011 and ISIC 2016). He has also served as Associate Editors of a number of journals, including IEEE Transactions of Circuits and Systems II – Brief Express (2018-2019) and (2019-2020), IEEE Transactions of Circuits and Systems I – Regular Papers (2012-2013), IEEE Transactions of Circuits and Systems II – Brief Express (2010-2011) and Journal of Circuits, Systems and Signal Processing (2007-2012). He was awarded Temasek Laboratories @ NTU Best Publication Award in 2012 and the Teaching Excellence Award (Year 3) in 2013. He was an IEEE Distinguished Lecture for Circuits and Systems Society in 2009-2010 and in 20172018. He was awarded the Singapore Defence Technology Prize in 2016.
Title: Hardware Attack and Assurance with Machine Learning: A Security Threat to Circuits and Systems
Abstract: Banking, defence applications and cryptosystems often demand security features, including cryptography, tamper resistance, stealth, and etc., by means of hardware approaches and/or software approaches to prevent data leakages. The hardware physical attacks or commonly known as side channel attacks have been employed to extract the secret keys of the encrypted algorithms implemented in hardware devices by analyzing their physical parameters such as power dissipation, electromagnetic interference and timing information. Altered functions or unauthorized modules may be added to the circuit design during the shipping and manufacturing process, bringing in security threats to the deployed systems. In this presentation, we will discuss hardware assurance from both device level and circuit level, and present how machine learning techniques can be utilized. At the device level, we will first provide an overview of the different cryptography algorithms and present the side channel attacks, particularly the powerful Correlation Power Analysis (CPA) and Correlation Electromagnetic Analysis (CEMA) with a leakage model that can be used to reveal the secret keys of the cryptosystems. We will then discuss several countermeasure techniques and present how highly secured microchips can be designed based on these techniques. At the circuit level, we will provide an overview of manufactured IC circuit analysis through invasive IC delayering and imaging. We then present several machine learning techniques that can be efficiently applied to the retrieval of circuit contact points and connections for further netlist/functional analysis.